? 1/9 august 1998 AN1001 application note choice of serial eeproms requires understanding of bus differences serial access memory devices offer many advantages over their parallel access counterparts. the list on the next page assumes the use of 10-bit addressing, as depicted in figure 1. the differential becomes even greater as the address space is increased. figure 1. serial access versus parallel access ai02471 data d1 chip enable parallel access eeprom (with 21 lines) data d2 data d3 data d4 data d5 data d6 data d7 address a0 address a1 address a2 address a3 address a4 address a5 address a6 address a8 address a9 data d0 address a7 write enable output enable ai02470 address/data clock serial access eeprom with 2-wire serial bus
AN1001 - application note 2/9 the advantages of serial access to the eeprom, or other slave devices, over parallel access, can be list- ed as follows: n fewer interconnect lines and pcb tracks: C a factor of 1/18th compared to the pcb area that is taken up by the ten address and eight data lines n fewer line buffers: C a factor of 1/18th comparing the pcb area that is taken up by address and data buffers C a factor of between 1/8th and 1/18th of the cost of address and data buffers (remembering that the address buffers of the parallel memory can be simple unidirectional devices) n fewer control lines: C a factor of 1/3rd, say, of the pcb area taken up by the control line pins of the chip n fewer interconnect pins: C a factor of 1/5th, say, of the pcb area taken up by the pins of the chip, and hence its footprint n fewer on-chip buffers: a factor of between 1/8th and 1/18th of the silicon area taken up by pads and i/o buffers for the address and data lines: C therefore, serial access memory devices have more silicon area available for increasing the mem- ory capacity, appearing on the market earlier than parallel access memory devices using compara- ble technology. the greatest disadvantage of serial access memory, of course, is access time. n lower data rate, due to the serial multiplexing of the single data line: C a factor of between 1/8th and 1/10th (depending on the number of stop and acknowledge bits) of the data transfer rate, during the data transfer cycles. C an even worse factor for the address transfer rate, partly because of the 10-bit address width, and partly because of the prefix instruction required to put the memory in its address-mode. for many applications, though, the access times of parallel access memory devices represent overkill C being unnecessarily fast for the requirements of the application. eeprom is not used like ram, and is used, in many applications, mainly for system parameter tables. these do not require very high speed ac- cess to the data for reading or writing, so serial bus speeds of 100 khz to 1 mhz are more than adequate. comparison of the four major serial access standards having decided that serial access eeprom is an appropriate choice for the application, the next design problem faced by the engineer is one of choosing the most appropriate serial bus standard. there are four main ones to choose from, each one available in stmicroelectronics memory products, and each offering differing capabilities in terms of bus size, bus protocol, noise immunity and access time. n i 2 c bus n xi 2 c bus n spi bus n microwire bus this document discusses these four standards, and the design trade-offs with which the application de- signer is faced when choosing between them.
3/9 AN1001 - application note i 2 c and xi 2 c buses perhaps the most popular of the four standards is the i 2 c bus, designed by philips. it was initially aimed at consumer applications market. a wide spectrum of devices is available today, not only memory devices. the i 2 c standard specifies a two-wire bus, as shown in figure 2. its sophisticated protocol allows systems to support many devices on the bus, with the capability even of allowing multiple masters, as well as mul- tiple slaves. the original i 2 c standard only allowed an address space of up to 16 kbit of memory, but the subsequent xi 2 c (extended i 2 c) bus standard, has extended this to 4 mbit. the bus speed is limited to 100 khz for i 2 c and 400 khz for xi 2 c. the noise immunity in both cases is good. figure 2. i 2 c and xi 2 c bus block diagram bus transfers start when the clock line is high on the falling edge of the data, as shown in figure 3. trans- fers are always 8 bits, followed by a ninth C an acknowledge bit from the bus receiver. data is transferred when the clock signal is high. the data line is wired or with an external pull-up resistor to v cc . figure 3. i 2 c and xi 2 c bus timing ai02477 v cc data clock i 2 c/xi 2 c eeprom write protect ai02474 clock 8 bits data data transfer when clock high start acknowledge
AN1001 - application note 4/9 spi bus the spi standard was first proposed by motorola, for its microcomputers, but is now offered by st and other companies, integrated as a peripheral into their mcus, and is rapidly gaining support. memories using this bus have four signal wires (data input, data output, clock and chip select), as shown in figure 4. each device on the bus must have its own, separate, chip select line. this means there is no limit to the number of slaves on one spi bus, but each increase demands another mcu i/o line. the max- imum bus speed is 5 mhz, and the noise immunity is very good. figure 4. spi bus block diagram bus transfers start after the chip select goes low, as shown in figure 5. transfers are always 8 bit, and each bit is detected on the rising edge of the clock. a write protect input is provided. figure 5. spi bus timing ai02475 data out data in clock spi eeprom write protect chip select ai02472 chip select clock bit 7 data bit 6
5/9 AN1001 - application note microwire ? the microwire bus is based on the system that was developed for the mcu products of national sem- iconductor. however, market support for this bus no longer appears to be growing. like the spi bus, it uses four wires and requires a chip select for each device on the bus, as shown in figure 6. the maximum bus speed is quite high, at 1 mhz. figure 6. microwire bus block diagram bus transfers start after chip select goes high. each data bit is detected on the rising edge of the clock, as shown in figure 7. a write enable input is provided on the s series devices. figure 7. microwire bus timing ai02476 data out data in clock microwire eeprom write protect ("s" series only) chip select ai02473 chip select clock most significant bit data
AN1001 - application note 6/9 the bus choices the choice of appropriate bus standard revolves round the following four major concerns: n the number of interface pins on the mcu: C here the i 2 c or xi 2 c buses are clear winners, since they need only two lines. n the system communication protocol: C for simple read or writes to the memory by an mcu, any of the bus types offers the same potential, but in a system where many different types of circuit are connected to the bus, or where a complex system of multi-masters/multi-slaves is used, only the i 2 c or xi 2 c can provide the necessary re- sources. n speed: C this is not a primary concern in many eeprom applications, but where it is important, the spi and microwire buses are favoured. n noise immunity, data security and protection from data corruption: C these concerns are not completely determined by the choice of bus standard. large differences exist between different manufacturers, and even between the different products from one manufac- turer. however, this issue is discussed further on the next page. data transfer speed and write completion polling the read data transfer speed of the serial buses varies from: n one byte every 1.6 m s for the spi with a 5 mhz clock n one byte every 8 m s for the microwire with a 1 mhz clock n one byte every 22.5 m s for the xi 2 c with a 400 khz clock. n one byte every 90 m s for the i 2 c with a 100 khz clock. all four standards support a burst mode, or sequential read mode, in which a contiguous block of any size can be read, one byte after another. i 2 c and xi 2 c types also support page write operations, allowing be- tween 8 and 32 consecutive bytes to be written in 5 to 10 ms. the spi standard is similar, but only the newer cs series of microwire devices offer a page write of 4 words (4x16 bits). the st specification, for all families of serial eeprom, states a maximum write time of 10 ms. however, the actual value, which is managed automatically and internally, is typically much faster than this. to take advantage of the faster typical write time in systems, designers use memory polling to detect when the write sequence has finished. the i 2 c and xi 2 c bus devices offer a very efficient polling system by detecting a memory acknowledge signal (a single bit that is sent by the eeprom, or other bus receiver, in the ninth bit time after the memory is addressed or data is exchanged). thus to poll the i 2 c devices, it is sufficient to send a single one byte address to the memory and to check the acknowledge bit that is sent response. for the spi bus, the polling technique requires that an internal status register be read to check a write-in- progress bit. this requires a read sequence of only two bytes length. the microwire devices can be polled by simply placing the chip select line high. a data output low in- dicates that writing is still in progress.
7/9 AN1001 - application note noise immunity and data security some defences, against noise and corrupt write commands, are applied automatically, internally within the device: n a low-pass filter on each input pin allows noise glitches to be ignored. n clock counting allows the device to time-out if the validity of the write operation becomes dubious (such as if it has exceeded the maximum specified duration). other defences can be applied only at the command of the external circuitry. this is potentially the strong- est defence since the external circuitry can be designed to monitor for quite elaborate conditions that are specific to the particular application. n the write control pin (wc) can be used to disable write sequences completely when conditions are unstable. n the user-defined read-only area, along with a previously set-up address pointer in the memory, can be used to make the selected block behave like rom. it is possible to overlap the effects of the internal and external defences. for example, de-assertion of the wc pin, during a write cycle on some devices, causes the internal write cycle to be aborted. this is a useful fail-safe defence if the source of the glitch on the wc line is also injecting noise on the data lines. table 1 shows the different memory ranges, capacities and features of sts serial eeproms. because of its better clock counting protocol, the xi 2 c standard offers good noise immunity. each 8-bit data transfer is accompanied by a ninth bit acknowledge by the device on the bus which is the current data receiver. moreover, a memory write cycle can only be triggered after both a correct series of acknowledg- es and a corresponding correct count of clock pulses. products that include an external write control input give added protection to the memory, especially during power up. these eeproms are desi gned to function even when v cc has dropped to 1.8 v, and can be functional as low as 1.5 v. however, because the mcu is not necessarily guaranteed to be functional at these volt- ages, random signals from the mcu can trigger spurious write cycles. this can be prevented by holding the write control inputs low, along with the mcu reset signal, until the bus signals are stable. both i 2 c (w series) and xi 2 c (e series) products from st feature write control inputs. in addition, the xi 2 c types in- clude an input filter on the data lines which rejects pulses narrower than 50 ns, thus filtering short noise glitches. table 1. st serial eeproms (in production or for release in 1995) bus type series capacity sequential read page write write control write protection i 2 c st24cxx 1 kbit-16 kbit x x 4 kbit-16 kbit st24wxx 1 kbit-16 kbit x x 4 kbit-16 kbit m24cxx 1 kbit-16 kbit x x x xi 2 c m24xxx 16 kbit-256 kbit x x x spi m95xxx 1 kbit-64 kbit x x x x microwire m93cxx 256 bit-4 kbit x x m93sxx 1 kbit-4 kbit x x x
AN1001 - application note 8/9 the i 2 c eeproms (st24cxx and st24wxx series, 4 kbit to 16 kbit capacities) also offer software programmed data protection. up to half of the memory can be made to behave like rom. a non-volatile register is set up to point to the address at which the write protection begins. of the two higher speed buses, spi and microwire, spi offers the better noise immunity and the great- er data protection. the spi protocol reads instructions, addresses and data from the bus by sampling on the rising edge of the clock. since all transfers are in 8-bit format, this allows an internal counter to inhibit writing to the memory should the chip select go high, to indicate the start of a write cycle, when the count is not a multiple of eight. additional immunity is provided by the instruction set which includes commands to enable a write control latch before a write cycle can begin. lastly, detection of an incorrect command instruction will automatically de-select the chip. data protection in the spi products is provided by both an external write protect input, like the i 2 c and xi 2 c devices, plus a programmable, non-volatile block protection scheme that allows zero, 25%, 50% or 75% of the total memory array to be write protected. the protocol of the microwire bus has several features that allow protection against spurious glitches on data or clock lines. two families of microwire products offer different levels data protection. the s family offers both a write enable input and programmable block write protection, in addition to the data protection features that were already provided in the older c family. the memory endurance a final consideration when choosing an eeprom device is its reliability after r epeated write/erase cycles. all types of non-volatile memory using floating-gate technology suffer from a gradual wear-out of the ox- ide. this leads to a deterioration of the cells ability to store a 1 or a 0, and hence to malfunction and loss of data. the endurance of the memory depends on the quality of the cmos manufacturing process, the technol- ogy and the memory cell design. st eeproms use a unique and very successful cell layout and process technology which is able to offer a performance of over one million write/erase cycles for medium capacity memory devices (up to 16 kbit). this is ten times better than competitive products, and even if not called for in the specific application, it can be viewed as an additional noise protection, as it guarantees much better security of memory retention during the lifetime of the equipment.
9/9 AN1001 - application note if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.eeprom@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 1998 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a.
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